Integrated circuit memory devices used for storing data can typically be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices generally lose any stored data when power supplied to the volatile memory device is interrupted. Nonvolatile memory devices typically retain any stored data even when power supplied to the nonvolatile memory device is interrupted. Accordingly, nonvolatile memory devices, such as flash memory devices have been widely used in, for example, memory cards, mobile telecommunication systems and the like, for their memory retention capabilities.
Information stored in a flash memory device may be electrically deleted or programmed. Generally, there are two types of flash memory devices, a NOR-type flash memory device and a NAND-type flash memory device. FIG. 1 illustrates a plan view of a conventional NOR-type flash memory device. Referring to FIG. 1, a device isolation layer (not shown) is provided on an integrated circuit substrate to define a plurality of active regions 100, for example, cell active regions 100a and source active region 100b. A plurality of word line patterns 104 is provided on the integrated circuit substrate and cross the active regions 100. Each of the word line patterns 104 includes a floating gate pattern 102, an inter-gate dielectric layer (not shown) and a control gate 103, which are sequentially stacked. Drain regions are provided in the cell active regions 100a along one sidewalls of the word line patterns 104 and bit line contact holes 108 are provided in the drain regions. A common source line 106, which is typically self-aligned to the word line patterns 104, is provided along the other sidewall of the word line patterns 104, and a common source contact hole 110 is provided in a region between the common source line 106 and the source active region 100b. A conductive material is provided in the bit line contact holes 108 to provide bit line contact plugs. Upper surfaces of the bit line contact plugs are electrically coupled to bit lines 112. The bit lines 112 are provided on the active cell regions 100a crossing the word line patterns 104. A conductive material is also provided in the common source contact hole 110 to provide a common source contact plug. An upper surface of the common source contact plug is electrically coupled to a common source contact wiring 114. The common source contact wiring 114 is provided on the source active region 100b parallel with the bit lines 112.
As illustrated in FIG. 1, a source contact hole is not formed for each unit cell of the flash memory device, a common source line 106 is formed instead. Accordingly, the width of the common source line 106 may be reduced, which may allow the size of the integrated circuit device to be reduced. However, in order to form the common source contact hole 110 such that it contacts the common source line 106 having the reduced width, the word line patterns 104 may be curved around the common source contact hole 110 as illustrated in FIG. 1.
As illustrated, the word line patterns 104 are curved at both sides of the common source contact hole 110. Thus, a distance d1 between the control gates 103 crossing over the active cell regions 100a adjacent to the common source contact hole 110 and the bit line contact holes 108 adjacent to the control gates 103, is smaller than a distance d2 between the control gates 103 on other active cell regions 100a and the bit line contact holes 108 adjacent to the control gates 103. Accordingly, coupling ratios between cells on the cell active regions 100a at both sides of the source active region 100b and cells on other cell active regions 100a may be different and may increase distribution of an erase threshold voltage of the NOR-type flash memory device.
Furthermore, the distance between floating gates 102 adjacent to both sides of the bit line contact holes 108 on the cell active regions 100a at both sides of the source active region 100b may be reduced and may reduce an alignment margin when the bit line contact holes are formed. Thus, if significant contact misalignment occurs, the bit line contact plug and the word line patterns 104 adjacent to both sides of the bit line contact plug may be electrically shorted, which may adversely affect the characteristics of the NOR-type flash memory device.